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integrated circuit systems, inc. ics950902 0475g?03/23/04 pin configuration recommended application: via p4x/p4m/kt/kn266/333 style chipsets. output features: 1 - pair of differential cpu clocks @ 3.3v (ck408)/ 1 - pair of differential open drain cpu clocks (k7) 1 - pair of differential push pull cpu_cs clocks @ 2.5v 3 - agp @ 3.3v 7 - pci @ 3.3v (1 - free running) 1 - 48mhz @ 3.3v fixed 1 - 24_48mhz @ 3.3v (default 48mhz i 2 c select only) 2 - ref @ 3.3v, 14.318mhz 12 - sdram (6 pair - ddr) selectable key specifications: ? cpu_cs - cput/c: <250ps cpu_cs - agp: <250ps cpu - ddr/sd: <250ps pci - pci: <500ps cpu - pci: min = 1.0ns, typ = 2.0ns, max = 4.0ns programmable timing control hub? for p4? * internal 120k pull-up resistor to vdd. ** internal 120k pull-down resistor to gnd. 56-pin 300-mil ssop & 240-mil tssop frequency table 0 l e s i t l u m t e g r a t d r a o b z m r e t / e c a r t , r e c n e r e f e r = f e r i v d d ) r r * 3 ( / t u p t u o t n e r r u c z @ h o v 0s m h o 0 5 , % 1 1 2 2 = r r a m 0 0 . 5 = f e r i f e r i * 4 = h o i0 5 @ v 0 . 1 1s m h o 0 5 , % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 5 @ v 7 . 0 3 s f2 s f1 s f0 s f k l c u p c z h m p g a z h m k l c i c p z h m 0000 0 0 . 0 6 10 0 . 0 80 0 . 0 4 0001 0 0 . 4 6 10 0 . 2 80 0 . 1 4 0010 0 6 . 6 6 10 6 . 6 60 3 . 3 3 0011 0 0 . 0 7 10 0 . 8 60 0 . 4 3 0100 0 0 . 5 7 10 0 . 0 70 0 . 5 3 0101 0 0 . 0 8 10 0 . 2 70 0 . 6 3 0110 0 0 . 5 8 10 0 . 4 70 0 . 7 3 0111 0 0 . 0 9 10 0 . 6 70 0 . 8 3 1000 0 8 . 6 60 8 . 6 60 4 . 3 3 1001 0 9 . 0 0 17 2 . 7 63 6 . 3 3 10 10 0 6 . 3 3 10 8 . 6 60 4 . 3 3 10 11 0 4 . 0 0 20 8 . 6 60 4 . 3 3 1100 0 6 . 6 60 6 . 6 60 3 . 2 3 1101 0 0 . 0 0 10 6 . 6 60 3 . 3 3 1110 0 0 . 0 0 20 6 . 6 60 3 . 3 3 1111 0 3 . 3 3 10 6 . 6 60 3 . 3 3 *fs0/ref0 1 56 vtt_pwrgd#**/ref1 gnd 2 55 vddref x1 3 54 gnd x2 4 53 cpuclkt/cpuclkodt vddagp 5 52 cpuclkc/cpuclkodc *mode/agpclk0 6 51 vddcpu3.3 *sel_408/k7/agpclk1 7 50 vddcpu2.5 *(pci_stop#)agpclk2 8 49 cpuc_cs gndagp 9 48 cput_cs **fs1/pciclk_f 10 47 gnd **sel_sdr/ddr#/pciclk1 11 46 fbout *multsel/pciclk2 12 45 buf_in gndpci 13 44 ddrt0/sdram0 pciclk3 14 43 ddrc0/sdram1 pciclk4 15 42 ddrt1/sdram2 vddpci 16 41 ddrc1/sdram3 pciclk517 40vdd3.3_2.5 *(clk_stop#)pciclk6 18 39 gnd gnd48 19 38 ddrt2/sdram4 *fs3/48mhz 20 37 ddrc2/sdram5 *fs2/24_48mhz 21 36 ddrt3/sdram6 avdd48 22 35 ddrc3/sdram7 vdd 23 34 vdd3.3_2.5 gnd 24 33 gnd iref 25 32 ddrt4/sdram8 *(pd#)reset# 26 31 ddrc4/sdram9 sclk 27 30 ddrt5/sdram10 sdata 28 29 ddrc5/sdram11 ics950902 features/benefits: programmable output frequency. programmable output divider ratios. programmable output rise/fall time. programmable output skew. programmable spread percentage for emi control. ddr output buffer supports up to 200mhz. watchdog timer technology to reset system if system malfunctions. programmable watch dog safe frequency. support i 2 c index read/write and block read/write operations. uses external 14.318mhz crystal.
2 integrated circuit systems, inc. ics950902 0475g?03/23/04 general description the ics950902 is a single chip clock solution for desktop designs using the via p4x/p4m/kt/kn266/333 style chipsets with pc133 or ddr memory. the ics950902 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). this part incorporates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. m/n control can configure output frequency with resolution up to 0.1mhz increment. block diagram ddrc (5:0)/sdram (10,8,6,4,2,0) ddrc (5:0)/sdram (11,9,7,5,3,1) fbout power groups vdd gnd 55 2 xtal, ref 5 9 agp [0:2], cpu digital, cpu pll 16 13 pci [0:5], pci_f outputs 22 19 48mhz, fix digital, fix analog 23 24 master clock, cpu analog 34, 40 33, 39 ddr/sdr outputs 50 47 2.5v cput/c_cs output 51 54 3.3v cput/c & cpuod_t/c pin number description
3 integrated circuit systems, inc. ics950902 0475g?03/23/04 pin description pin description continued on next page. pin pin pin # name type 1 *fs0/ref0 i/o frequency select latch input pin / 14.318 mhz reference clock. 2 gnd pwr ground pin. 3 x1 in cr y stal in p ut,nominall y 14.318mhz. 4 x2 out cr y stal out p ut, nominall y 14.318mhz 5 vddagp pwr power su pp l y for agp clocks, nominal 3.3v 6 *mode/agpclk0 i/o function select latch input pin, 1=desktop mode, 0=mobile mode / agp clock output. 7 *sel_408/k7/agpclk1 i/o cpu out p ut t yp e select latch in p ut p in 0= k7, 1= ck408 / agp clock out p ut. 8 *(pci_stop#)agpclk2 i/o stops all pciclks besides the pciclk_f clocks at logic 0 level, when input low. this input is activated b y the mode selection p in / agp clock out p ut. 9 gndagp pwr ground p in for the agp out p uts 10 **fs1/pciclk_f i/o fre q uenc y select latch in p ut p in / 3.3v pci free runnin g clock out p ut. 11 **sel_sdr/ddr#/pciclk1 i/o memory type select latch input pin 0= ddr, 1= pc133 sdram / 3.3v pci clock output. 12 *multsel/pciclk2 i/o 3.3v lvttl input for selection the current multiplier for cpu outputs / 3.3v pci clock output. 13 gndpci pwr ground p in for the pci out p uts 14 pciclk3 out pci clock out p ut. 15 pciclk4 out pci clock out p ut. 16 vddpci pwr power su pp l y for pci clocks, nominal 3.3v 17 pciclk5 out pci clock out p ut. 18 *(clk_stop#)pciclk6 i/o stops all cpu, ddr/sdram and fb_out clocks at logic 0 level, when input low. this input is activated b y the mode selection p in / pci clock out p ut. 19 gnd48 pwr ground p in for the 48mhz out p uts 20 *fs3/48mhz i/o fre q uenc y select latch in p ut p in / fixed 48mhz clock out p ut. 3.3v 21 *fs2/24_48mhz i/o fre q uenc y select latch in p ut p in / fixed 24 or 48mhz clock out p ut. 3.3v. 22 avdd48 pwr power for 24/48mhz out p uts and fixed pll core, nominal 3.3v 23 vdd pwr power su pp l y , nominal 3.3v 24 gnd pwr ground p in. 25 iref out this pin establishes the reference current for the cpuclk pairs. this pin requires a fixed p recision resistor tied to g round in order to establish the a pp ro p riate current. 26 *(pd#)reset# i/o asynchronous active low input pin used to power down the device into a low power state. this input is activated by the mode selection pin / real time system reset signal for frequency gear ratio change or watchdog timer timeout. this signal is active low. 27 sclk in clock p in of i2c circuitr y 5v tolerant 28 sdata i/o data pin for i2c circuitry 5v tolerant * internal pull-up resistor ** internal pull-down resistor description ~ this output has 2x drive strength
4 integrated circuit systems, inc. ics950902 0475g?03/23/04 pin description continued pin pin pin # name type 29 ddrc5/sdram11 out "com p lementar y " clock of differential memor y out p ut / 3.3v sdram clock out p ut 30 ddrt5/sdram10 out "true" clock of differential memor y out p ut / 3.3v sdram clock out p ut 31 ddrc4/sdram9 out "com p lementar y " clock of differential memor y out p ut / 3.3v sdram clock out p ut 32 ddrt4/sdram8 out "true" clock of differential memor y out p ut / 3.3v sdram clock out p ut 33 gnd pwr ground p in. 34 vdd3.3_2.5 pwr 2.5v or 3.3v nominal p ower su pp l y volta g e. 35 ddrc3/sdram7 out "com p lementar y " clock of differential memor y out p ut / 3.3v sdram clock out p ut 36 ddrt3/sdram6 out "true" clock of differential memor y out p ut / 3.3v sdram clock out p ut 37 ddrc2/sdram5 out "com p lementar y " clock of differential memor y out p ut / 3.3v sdram clock out p ut 38 ddrt2/sdram4 out "true" clock of differential memor y out p ut / 3.3v sdram clock out p ut 39 gnd pwr ground p in. 40 vdd3.3_2.5 pwr 2.5v or 3.3v nominal p ower su pp l y volta g e. 41 ddrc1/sdram3 out "com p lementar y " clock of differential memor y out p ut / 3.3v sdram clock out p ut 42 ddrt1/sdram2 out "true" clock of differential memor y out p ut / 3.3v sdram clock out p ut 43 ddrc0/sdram1 out "com p lementar y " clock of differential memor y out p ut / 3.3v sdram clock out p ut 44 ddrt0/sdram0 out "true" clock of differential memor y out p ut / 3.3v sdram clock out p ut 45 buf_in in in p ut buffers for memor y out p uts. 46 fbout out memor y feed back out p ut. 47 gnd pwr ground p in. 48 cput_cs out "true" clocks of differential p air 2.5v p ush- p ull cpu out p uts. 49 cpuc_cs out com p lementar y " clocks of differential p air 2.5v p ush- p ull cpu out p uts. 50 vddcpu2.5 pwr power p in for the cpuclks. 2.5v 51 vddcpu3.3 pwr power p in for the cpuclks. 3.3v 52 cpuclkc/cpuclkodc out "complementary" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias / "complementary" clocks of differential pair cpu outputs. these open drain outputs need an external 1.5v pull-up / 2.5v cpu clock out p ut. 53 cpuclkt/cpuclkodt out "true" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias / "true" clocks of differential pair cpu outputs. these open drain outputs need an external 1.5v pull-up / 2.5v cpu clock output. 54 gnd pwr ground p in. 55 vddref pwr ref, xtal p ower su pp l y , nominal 3.3v 56 vtt_pwrgd#**/ref1 in this 3.3v lvttl input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. this is an active low input. / 14.318 mhz reference clock. description mode pin - power management input control 6 n i p , e d o m ) t u p n i d e h c t a l ( 6 2 n i p8 1 n i p8 n i p 0 # d p ) t u p n i ( # p o t s _ k l c ) t u p n i ( # p o t s _ i c p ) t u p n i ( 1 # t e s e r ) t u p t u o ( 6 k l c i c p ) t u p t u o ( 2 p g a ) t u p t u o (
5 integrated circuit systems, inc. ics950902 0475g?03/23/04 general i 2 c serial interface information how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit *see notes on the following page . ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
6 integrated circuit systems, inc. ics950902 0475g?03/23/04 byte 0: functionality and frequency select register (default=0) notes: 1. default at power-up will be for latched logic inputs to define frequency, as displayed by bit 3. t i b n o i t p i r c s e d d w p t i b ) 4 : 7 , 2 ( 2 t i b7 t i b6 t i b5 t i b4 t i b k l c u p c z h m k l c p g a z h m k l c i c p z h m % d a e r p s 1 e t o n 4 s f3 s f2 s f1 s f0 s f 00000 0 0 . 2 0 10 0 . 8 60 0 . 4 3d a e r p s r e t n e c % 0 3 . 0 - / + 0000 1 0 0 . 5 0 10 0 . 0 70 0 . 5 3d a e r p s r e t n e c % 0 3 . 0 - / + 00010 0 0 . 8 0 10 0 . 2 70 0 . 6 3d a e r p s r e t n e c % 0 3 . 0 - / + 00011 0 0 . 1 1 10 0 . 4 70 0 . 7 2d a e r p s r e t n e c % 0 3 . 0 - / + 00 100 0 0 . 4 1 10 0 . 6 70 0 . 8 3d a e r p s r e t n e c % 0 3 . 0 - / + 00 10 1 0 0 . 7 1 10 0 . 8 70 0 . 9 3d a e r p s r e t n e c % 0 3 . 0 - / + 00 110 0 0 . 0 2 10 0 . 0 80 0 . 0 4d a e r p s r e t n e c % 0 3 . 0 - / + 00 111 0 0 . 3 2 10 0 . 2 80 0 . 1 4d a e r p s r e t n e c % 0 3 . 0 - / + 01000 0 0 . 6 2 10 0 . 2 70 0 . 6 3d a e r p s r e t n e c % 0 3 . 0 - / + 01001 0 0 . 0 3 10 3 . 4 70 1 . 7 3d a e r p s r e t n e c % 0 3 . 0 - / + 01010 0 9 . 3 3 15 9 . 6 68 4 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 01011 0 0 . 0 4 10 0 . 0 70 0 . 5 3d a e r p s r e t n e c % 0 3 . 0 - / + 01100 0 0 . 4 4 10 0 . 2 70 0 . 6 3d a e r p s r e t n e c % 0 3 . 0 - / + 01101 0 0 . 8 4 10 0 . 4 70 0 . 7 3d a e r p s r e t n e c % 0 3 . 0 - / + 01110 0 0 . 2 5 10 0 . 6 70 0 . 8 3d a e r p s r e t n e c % 0 3 . 0 - / + 01111 0 0 . 6 5 10 0 . 8 70 0 . 9 3d a e r p s r e t n e c % 0 3 . 0 - / + 10 00 0 0 0 . 0 6 10 0 . 0 80 0 . 0 4d a e r p s r e t n e c % 0 3 . 0 - / + 10 00 1 0 0 . 4 6 10 0 . 2 80 0 . 1 4d a e r p s r e t n e c % 0 3 . 0 - / + 10 0 10 0 6 . 6 6 10 6 . 6 60 3 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 10 0 1 1 0 0 . 0 7 10 0 . 8 60 0 . 4 3d a e r p s r e t n e c % 0 3 . 0 - / + 10 10 0 0 0 . 5 7 10 0 . 0 70 0 . 5 3d a e r p s r e t n e c % 0 5 . 0 - / + 10 10 1 0 0 . 0 8 10 0 . 2 70 0 . 6 3d a e r p s r e t n e c % 0 5 . 0 - / + 10 110 0 0 . 5 8 10 0 . 4 70 0 . 7 3d a e r p s r e t n e c % 0 5 . 0 - / + 10 11 1 0 0 . 0 9 10 0 . 6 70 0 . 8 3d a e r p s r e t n e c % 0 3 . 0 - / + 11000 0 8 . 6 60 8 . 6 60 4 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 1100 1 0 9 . 0 0 17 2 . 7 63 6 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 11010 0 6 . 3 3 10 8 . 6 60 4 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 11011 0 4 . 0 0 20 8 . 6 60 4 . 3 3d a e r p s r e t n e c % 0 3 . 0 - / + 11100 0 6 . 6 60 6 . 6 60 3 . 2 3d a e r p s n w o d % 6 . 0 - o t 0 1110 1 0 0 . 0 0 10 6 . 6 60 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 11110 0 0 . 0 0 20 6 . 6 60 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 11111 0 3 . 3 3 10 6 . 6 60 3 . 3 3d a e r p s n w o d % 6 . 0 - o t 0 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
7 integrated circuit systems, inc. ics950902 0475g?03/23/04 byte 1: cpu active/inactive register (1 = enable, 0 = disable) byte 3: active/inactive register (1 = enable, 0 = disable) byte 2: pci active/inactive register (1 = enable, 0 = disable) byte 4: frequency select active/inactive register (1 = enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b6 41 t u o _ b f) e v i t c a n i / e v i t c a ( 6 t i b-1 z h m 8 4 = 1 z h m 4 2 = 0 , 8 4 _ 4 2 l e s 5 t i b-1 g n i n n u r e e r f t o n 0 ; g n i n n u r e e r f = 1 ; l o r t n o c g n i n n u r e e r f r d d / d s 4 t i b6 511 f e r) e v i t c a n i / e v i t c a ( 3 t i b9 4 , 8 41 g n i n n u r e e r f t o n 0 ; g n i n n u r e e r f = 1 ; l o r t n o c g n i n n u r e e r f s c _ t / c u p c 2 t i b81 2 k l c p g a) e v i t c a n i / e v i t c a ( 1 t i b71 ) e v i t c a n i / e v i t c a ( 1 k l c p g a 0 t i b61 0 k l c p g a) e v i t c a n i / e v i t c a ( t i b# n i pd w pn o i t p i r c s e d 7 t i b9 21 ) e v i t c a n i / e v i t c a ( 5 c r d d / 1 1 m a r d s 6 t i b0 11 ) e v i t c a n i / e v i t c a ( f _ k l c i c p 5 t i b0 31 ) e v i t c a n i / e v i t c a ( 5 t r d d / 0 1 m a r d s 4 t i b1 31 ) e v i t c a n i / e v i t c a ( 4 c r d d / 9 m a r d s 3 t i b-1 ) d e v r e s e r ( 2 t i b2 31 ) e v i t c a n i / e v i t c a ( 4 t r d d / 8 m a r d s 1 t i b2 5 , 3 51 ) e v i t c a n i / e v i t c a ( s c _ c / t k l c u p c 0 t i b9 4 , 8 41 ) e v i t c a n i / e v i t c a ( s c _ c / t k l c u p c t i b# n i pd w pn o i t p i r c s e d 7 t i b-x 3 s f d e h c t a l 6 t i b-x 2 s f d e h c t a l 5 t i b-x 1 s f d e h c t a l 4 t i b-x 0 s f d e h c t a l 3 t i b0 21 ) e v i t c a n i / e v i t c a ( z h m 8 4 2 t i b1 21 ) e v i t c a n i / e v i t c a ( z h m 8 4 _ 4 2 1 t i b-- ) d e v r e s e r ( 0 t i b11 ) e v i t c a n i / e v i t c a ( 0 f e r t i b# n i pd w pn o i t p i r c s e d 7 t i b6 41 g n i n n u r e e r f t o n = 0 ; g n i n n u r e e r f = 1 ; l o r t n o c g n i n n u r e e r f t u o _ b f 6 t i b8 11 ) e v i t c a n i / e v i t c a ( 6 k l c i c p 5 t i b7 11 ) e v i t c a n i / e v i t c a ( 5 k l c i c p 4 t i b5 11 ) e v i t c a n i / e v i t c a ( 4 k l c i c p 3 t i b4 11 ) e v i t c a n i / e v i t c a ( 3 k l c i c p 2 t i b2 11 ) e v i t c a n i / e v i t c a ( 2 k l c i c p 1 t i b1 11 ) e v i t c a n i / e v i t c a ( 1 k l c i c p 0 t i b2 5 , 3 51 g n i n n u r e e r f t o n = 0 ; g n i n n u r e e r f = 1 ; l o r t n o c g n i n n u r e e r f c / t k l c u p c
8 integrated circuit systems, inc. ics950902 0475g?03/23/04 byte 7: revision id and device id register byte 8: byte count read back register byte 5: peripheral active/inactive register (1 = enable, 0 = disable) byte 6: vendor id register (1 = enable, 0 = disable) t i be m a nd w pn o i t p i r c s e d 7 t i b7 e t y b0 w o h d n a t n u o c e t y b e r u g i f n o c l l i w r e t s i g e r s i h t o t g n i t i r w : e t o n s i t l u a f e d , k c a b d a e r e b l l i w s e t y b y n a mf 0 h . s e t y b 5 1 = 6 t i b6 e t y b0 5 t i b5 e t y b0 4 t i b4 e t y b0 3 t i b3 e t y b1 2 t i b2 e t y b1 1 t i b1 e t y b1 0 t i b0 e t y b1 t i be m a nd w pn o i t p i r c s e d 7 t i b3 t i b d i n o i s i v e rx n o i s i v e r s ' e c i v e d l a u d i v i d n i n o d e s a b e b l l i w s e u l a v d i n o i s i v e r 6 t i b2 t i b d i n o i s i v e rx 5 t i b1 t i b d i n o i s i v e rx 4 t i b0 t i b d i n o i s i v e rx 3 t i b3 t i b d i r o d n e v0) d e v r e s e r ( 2 t i b2 t i b d i r o d n e v0) d e v r e s e r ( 1 t i b1 t i b d i r o d n e v0) d e v r e s e r ( 0 t i b0 t i b d i r o d n e v1) d e v r e s e r ( t i b# n i pd w pn o i t p i r c s e d 7 t i b5 31 ) e v i t c a n i / e v i t c a ( 3 c r d d / 7 m a r d s 6 t i b6 31 ) e v i t c a n i / e v i t c a ( 3 t r d d / 6 m a r d s 5 t i b7 31 ) e v i t c a n i / e v i t c a ( 2 c r d d / 5 m a r d s 4 t i b8 31 ) e v i t c a n i / e v i t c a ( 2 t r d d / 4 m a r d s 3 t i b1 41 ) e v i t c a n i / e v i t c a ( 1 c r d d / 3 m a r d s 2 t i b2 41 ) e v i t c a n i / e v i t c a ( 1 t r d d / 2 m a r d s 1 t i b3 41 ) e v i t c a n i / e v i t c a ( 0 c r d d / 1 m a r d s 0 t i b4 41 ) e v i t c a n i / e v i t c a ( 0 t r d d / 0 m a r d s t i be m a nd w pn o i t p i r c s e d 7 t i b7 d i e c i v e d0 e c i v e d l a u d i v i d n i n o d e s a b e b l l i w s e u l a v d i e c i v e d . e s a c s i h t n i " h 1 0 " 6 t i b6 d i e c i v e d0 5 t i b5 d i e c i v e d0 4 t i b4 d i e c i v e d1 3 t i b3 d i e c i v e d0 2 t i b2 d i e c i v e d1 1 t i b1 d i e c i v e d1 0 t i b0 d i e c i v e d1
9 integrated circuit systems, inc. ics950902 0475g?03/23/04 byte 10: programming enable bit 8 watchdog control register byte 11: vco frequency m divider (reference divider) control register byte 12: vco frequency n divider (vco divider) control register byte 9: watchdog timer count register t i be m a nd w pn o i t p i r c s e d 7 t i b8 v i d nx 8 t i b r e d i v i d n 6 t i b6 v i d mx e h t o t d s o p s e r r o c ) 0 : 6 ( v i d m f o n o i t a t n e s e r p s e r l a m i c e d e h t e h t o t l a u q e s i p u r e w o p t a t l u a f e d . e u l a v r e d i v i d e c n e r e f e r . n o i t c e l e s s t u p n i d e h c t a l 5 t i b5 v i d mx 4 t i b4 v i d mx 3 t i b3 v i d mx 2 t i b2 v i d mx 1 t i b1 v i d mx 0 t i b0 v i d mx t i be m a nd w pn o i t p i r c s e d 7 t i b7 v i d nx e h t o t d n o p s e r r o c ) 0 : 8 ( v i d n f o n o i t a t n e s e r p e r l a m i c e d e h t e h t o t l a u q e s i p u r e w o p t a t l u a f e d . e u l a v r e d i v i d o c v . 1 1 e t y b n i d e t a c o l s i 8 v i d n e c i t o n . n o t c e l e s s t u p n i d e h c t a l 6 t i b6 v i d nx 5 t i b5 v i d nx 4 t i b4 v i d nx 3 t i b3 v i d nx 2 t i b2 v i d nx 1 t i b1 v i d nx 0 t i b0 v i d nx t i be m a nd w pn o i t p i r c s e d 7 t i b7 d w0 x o t d n o p s e r r o c s t i b 8 e s e h t f o n o i t a t n e s e r p e r l a m i c e d e h t e d o m m r a l a o t s e o g t i e r o f e b t i a w l l i w r e m i t g o d h c t a w e h t s m 0 9 2 s i p u r e w o p t a t l u a f e d . g n i t t e s e f a s e h t o t y c n e u q e r f e h t t e s e r d n a . s d n o c e s 6 . 4 = s m 0 9 2 6 1 6 t i b6 d w0 5 t i b5 d w0 4 t i b4 d w0 3 t i b3 d w1 2 t i b2 d w0 1 t i b1 d w0 0 t i b0 d w0 t i be m a nd w pn o i t p i r c s e d 7 t i b m a r g o r p e l b a n e 0 t i b e l b a n e g n i m m a r g o r p 1 0 e t y b r o s e h c t a l w h y b d e t c e l e s e r a s e i c n e u q e r f . g n i m m a r g o r p o n = 0 i l l a e l b a n e = 2 . g n i m a r g o r p c 6 t i be l b a n e d w0 . t i b e l b a n e g o d h c t a w e r a w t f o s . e l b a n e = 1 , e l b a s i d = 0 . e u l a v d e h c t a l n e d w e t i r w r e v o l l i w t i b s i h t 5 t i bm r a l a d w0 s u t a t s m r a l a = 1 l a m r o n = 0 s u t a t s m r a l a g o d h c t a w 4 t i b4 f s0 e f a s e h t e r u g i f n o c l l i w s t i b e s e h t o t g n i t i r w . s t i b y c n e u q e r f e f a s g o d h c t a w e l b a t 4 : 7 , 2 t i b 0 e t y b o t g n i d n o p s r r o c y c n e u q e r f 3 t i b3 f s0 2 t i b2 f s0 1 t i b1 f s0 0 t i b0 f s1
10 integrated circuit systems, inc. ics950902 0475g?03/23/04 byte 14: spread spectrum control register byte 15: output divider control register byte 13: spread spectrum control register byte 16: output divider control register t i be m a nd w pn o i t p i r c s e d 7 t i b7 s sx d a e r p s e h t m a r g o r p l l i w t i b ) 0 : 2 1 ( m u r t c e p s d a e r p s e h t e h t n o d e s a b d e t a l u c l a c e b o t s d e e n t n e c e r p d a e r p s . e g a t n e c e r p d a e r p s d n a t n u o m a g n i d a e r p s , e l i f o r p g n i d a e r p s , y c n e u q e r f o c v d a e r p s r o f e r a w t f o s s c i e s u o t d e d n e m m o c e r s i t i . y c n e u q e r f . r e d i v i d s f d e h c t a l s i n o r e w o p t l u a f e d . g n i m m a r g o r p 6 t i b6 s sx 5 t i b5 s sx 4 t i b4 s sx 3 t i b3 s sx 2 t i b2 s sx 1 t i b1 s sx 0 t i b0 s sx t i be m a nd w pn o i t p i r c s e d 7 t i bd e v r e s e rxd e v r e s e r 6 t i bd e v r e s e rxd e v r e s e r 5 t i bd e v r e s e rxd e v r e s e r 4 t i b2 1 s sx 2 1 t i b m u r t c e p s d a e r p s 3 t i b1 1 s sx 1 1 t i b m u r t c e p s d a e r p s 2 t i b0 1 s sx 0 1 t i b m u r t c e p s d a e r p s 1 t i b9 s sx 9 t i b m u r t c e p s d a e r p s 0 t i b8 s sx 8 t i b m u r t c e p s d a e r p s t i be m a nd w pn o i t p i r c s e d 7 t i b3 v i d p g a0 4 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c p g a o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t 6 t i b2 v i d p g a1 5 t i b1 v i d p g a0 4 t i b0 v i d p g a1 3 t i bd e v r e s e r- d e v r e s e r 2 t i bd e v r e s e r- 1 t i bd e v r e s e r- 0 t i bd e v r e s e r- t i be m a nd w pn o i t p i r c s e d 7 t i b3 v i d u p c0 a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c t / c k l c u p c r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 e s e h t . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t o t 6 t i b2 v i d u p c1 5 t i b1 v i d u p c0 4 t i b0 v i d u p c1 3 t i b3 v i d u p c0 d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c s c _ c / t k l c u p c e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i s t i b 4 e s e h t a i v s f d e h c t a l s i p u r e w o p t a t l u a f e d . 1 e l b a t o t r e f e r . r e d i v i d 2 t i b2 v i d u p c1 1 t i b1 v i d u p c0 0 t i b0 v i d u p c1
11 integrated circuit systems, inc. ics950902 0475g?03/23/04 byte 17: output divider control register byte 18: group skew control register byte 19: group skew control register table 1 table 2 ) 2 : 3 ( v i d 0 01 00 11 1 ) 0 : 1 ( v i d 0 02 /4 /8 /6 1 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 17 /4 1 /8 2 /6 5 / ) 2 : 3 ( v i d 0 01 00 11 1 ) 0 : 1 ( v i d 0 04 /8 /6 1 /2 3 / 1 03 /6 /2 1 /4 2 / 0 15 /0 1 /0 2 /0 4 / 1 19 /8 1 /6 3 /2 7 / t i be m a nd w pn o i t p i r c s e d 7 t i b d e v r e s e r 1 d e v r e s e r 6 t i b0 5 t i b0 4 t i b0 3 t i b ) 0 : 5 ( k l c i c p w e k s p u o r g l o r t n o c 1 - s n 4 . 1 m o r f w e k s ) 0 : 5 ( i c p o t u p c e h t e g n a h c n a c s t i b 4 e s e h t r o t n e m e r c n i y r a n i b h c a e . s n 5 . 2 - s i p u r e w o p t a t l u a f e d . s n 9 . 2 e h t f o y a l e d e h t e s a e r c e d r o e s a e r c n i l l i w ) 0 : 3 ( s t i b f o t n e m e r c e d . s p 0 0 1 y b s k c o l c i c p 2 t i b0 1 t i b0 0 t i b0 t i be m a nd w pn o i t p i r c s e d 7 t i b s c _ c / t k l c u p c w e k s p u o r g l o r t n o c 1 o t t c e p s e r h t i w s c _ c / t k l c u p c e h t y a l e d s t i b 2 e s e h t s c _ c / t k l c u p c s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 s p 0 5 2 = 1 0 s p 0 = 0 0 6 t i b0 5 t i b c / t k l c u p c w e k s p u o r g l o r t n o c 1 e h t y a l e d s t i b 2 e s e h tc / t k l c u p co t t c e p s e r h t i w k c o l c s c _ c / t k l c u p c s p 0 5 2 = 1 0 s p 0 = 0 0s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 4 t i b0 3 t i b k l c p g a w e k s p u o r g l o r t n o c 1 l c p g a e h t y a l e d s t i b 2 e s e h tko t t c e p s e r h t i w s k c o l ck l c u p c s p 0 5 2 = 1 0 s p 0 = 0 0s p 0 5 7 = 1 1 s p 0 0 5 = 0 1 2 t i b0 1 t i bd e v r e s e rxd e v r e s e r 0 t i bd e v r e s e rxd e v r e s e r t i be m a nd w pn o i t p i r c s e d 7 t i bv n i _ p g a0 t i b n o i s r e v n i e s a h p p g a 6 t i bd e v r e s e r0d e v r e s e r 5 t i bv n i _ u p c0 t i b n o i s r e v n i e s a h p c / t u p c 4 t i bv n i _ u p c0 t i b n o i s r e v n i e s a h p s c _ c / t u p c 3 t i b 3 v i d i c p1 s t i b 4 e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c i c p . 2 e l b a t o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o f . y l l a u d i v i d n i . r e d i v i d s f d e h c t a l s i p u r e w o p t a t l u a f e d 2 t i b 2 v i d i c p0 1 t i b 1 v i d i c p0 0 t i b 0 v i d i c p1
12 integrated circuit systems, inc. ics950902 0475g?03/23/04 byte 20: group skew control register byte 21: slew rate control register byte 22: slew rate control register byte 23: slew rate control register t i be m a nd w pn o i t p i r c s e d 7 t i b f _ k l c i c p w e k s p u o r g l o r t n o c 1 - s n 4 . 1 m o r f w e k s f i c p o t u p c e h t e g n a h c n a c s t i b 4 e s e h t r o t n e m e r c n i y r a n i b h c a e . s n 5 . 2 - s i p u r e w o p t a t l u a f e d . s n 9 . 2 e h t f o y a l e d e h t e s a e r c e d r o e s a e r c n i l l i w ) 0 : 3 ( t i b f o t n e m e r c e d . s p 0 0 1 y b s k c o l c i c p 6 t i b0 5 t i b0 4 t i b0 3 t i b d e v r e s e r 1 d e v r e s e r 2 t i b0 1 t i b0 0 t i b0 t i be m a nd w pn o i t p i r c s e d 7 t i b ) 1 : 2 ( p g a l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c ) 1 : 2 ( p g a k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 6 t i b1 5 t i b f _ k l c i c p l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c f _ k l c i c p k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 4 t i b1 3 t i b ) 4 : 7 ( k l c i c p l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c ) 4 : 7 ( k l c i c p k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 2 t i b1 1 t i b ) 0 : 3 ( k l c i c p l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c ) 0 : 3 ( k l c i c p k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 0 t i b1 t i be m a nd w pn o i t p i r c s e d 7 t i b f e r l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c f e r k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 6 t i b1 5 t i b ) 0 : 1 ( c i p a o i l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c ) 0 : 1 ( c i p a o i k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 4 t i b1 3 t i b z h m 8 4 l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c z h m 8 4 k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 2 t i b1 1 t i b z h m 8 4 _ 4 2 l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c z h m 8 4 _ 4 2 k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 0 t i b1 t i be m a nd w pn o i t p i r c s e d 7 t i b s c _ c / t k l c u p c l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c s c _ c / t k l c u p c k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 6 t i b1 5 t i b 1 c / 1 t k l c u p c l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c 1 c / 1 t k l c u p c k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 4 t i b1 3 t i b 2 c / 2 t k l c u p c l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c 2 c / 2 t k l c u p c k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 2 t i b1 1 t i b 0 _ p g a l o r t n o c e t a r w e l s 0 . s t i b l o r t n o c e t a r w e l s k c o l c 0 _ p g a k a e w = 0 0 ; l a m r o n = 0 1 : g n o r t s = 1 0 0 t i b1
13 integrated circuit systems, inc. ics950902 0475g?03/23/04 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics- input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3v +-5% parameter symbol conditions min typ max units input high voltage v ih 2v d d + 0.3 v input low voltage v il v ss - 0.3 0.8 v input high current i ih v in =v dd -5 5 ma input low current i il1 vi n = 0 v; inputs with no pull-up resistors -5 ma input low current i il2 v in = 0 v; inputs with no pull-up resistors -200 ma c l = 0 pf; select @ 66m 100 ma c l = full load @ 133mhz 156 280 ma iref=2.32 10 20 ma iref= 5ma 37 ma input frequency f i v d d =3.3v; mhz pin inductance l p in 7nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time1 t trans to 1st crossing of target freq. 3 ms settling time1 t s from 1st crossing to 1% target freq. 3 ms clk stabilization1 t stab from v dd = 3.3 v to 1% target freq. 3 ms t pzh ,t pzh output enable delay (all outputs) 1 10 ns t pl z ,t pzh output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. capacitance1 delay i dd3.3op operating supply current power down supply current i dd3.3pd
14 integrated circuit systems, inc. ics950902 0475g?03/23/04 electrical characteristics-cpuclkc/t t a = 0 - 70c; v d d = 3.3 v +/-5%; (unless otherwise stated) parameter symbol conditions min typ max units current source output impedance z o v o = v x 3000 ohm output high voltage v oh 0.81 1.2 v output high current i oh -13.92 ma rise time 1 t r v ol = 20%, v oh = 80% 175 270 700 ps differential crossover voltage 1 v x 45 50 55 % dut y c y cle 1 d t v t = 50% 45 50.2 55 % skew 1 , cpu to cpu t sk v t = 50% 55 150 ps jitter, cycle-to-cycle 1 t j c y c-c y c v t = v x 81 200 ps notes: 1 - guaranteed by design, not 100% tested in production. v r = 475w +1%; iref= 2.32ma; i oh = 6*iref electrical characteristics- cpuclkt/c_cs t a = 0 - 70c; v d d =2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2b i oh = -12.0 ma 2 v output low voltage v ol2b i ol = 12 ma 0.4 v output high current i oh2b v oh = 1.7 v -19 ma output low current i ol2b v ol = 0.7 v 19 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.89 1.6 ns differential crossover volta g e 1 v x 45 50 55 % duty cycle d t2b 1 v t = 1.25 v 45 49.6 55 % skew t sk2b 1 v t = 1.25 v 175 ps jitter, cycle-to-cycle t j c y c-c y c2b 1 v t = 1.25 v 72 250 ps jitter, one sigma t j 1s2b 1 v t = 1.25 v 150 ps jitter, absolute t j abs2b 1 v t = 1.25 v -250 250 ps 1 guaranteed by design, not 100% tested in production.
15 integrated circuit systems, inc. ics950902 0475g?03/23/04 electrical characteristics- sdram t a = 0 - 70c; v d d = 3.3v +/-5%, v ddl = 2.5v +/-5%; c l = 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh3 i oh = -28 ma 2.4 v output low voltage v ol3 i ol = 20 ma 0.4 v output high current i oh3 v oh = 2.0 v -40 ma output low current i ol3 v ol = 0.8 v 41 ma rise time1 t r3 v ol = 0.4 v, v oh = 2.4 v @ 100mhz 1.53 2 ns fall time1 t f3 v oh = 2.4 v, v ol = 0.4 v @ 100mhz 1.62 2 ns duty cycle1 d t3 v t = 1.5 v 45 50.2 55 % skew window1 t sk3 v t = 1.5 v 210 250 ps propagation time 1 (buffer in to output) t prop v t = 1.5 v 5.6 6 ns 1 guaranteed by design, not 100% tested in production. electrical characteristics- ddrt/c t a = 0 - 70c; v ddl =2.5 v +/-5%, c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh3 i oh = -11 ma 2 2282 v output low voltage v ol3 i ol = 11 ma 0.335 0.4 v output high current i oh3 v oh = 2.0 v -12 ma output low current i ol3 v ol = 0.8 v 12 ma rise time 1 t r3 1 20% to 80% 0.86 2.2 ns fall time 1 t f3 1 80% to 20% 0.65 2.2 ns duty cycle 1 d t3 1 v t = 50% 47 50.2 53 % skew (window) t sk 1 v t = 50% 81 250 ps jitter t j c y c-c y c 1 v t = 1.5 v 146 250 ps 1 guaranteed by design, not 100% tested in production.
16 integrated circuit systems, inc. ics950902 0475g?03/23/04 electrical characteristics - pciclk t a = 0 - 70c; v d d = 3.3v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f 01 33.33 mhz output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -33 -33 ma output low current i ol1 v ol @ min = 1.95 v, v ol @ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.92 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.92 2 ns duty cycle d t1 1 v t = 1.5 v 45 51 55 % skew t sk1 1 v t = 1.5 v 150 500 ps jitter t j c y c-c y c1 v t = 1.5 v 157 250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - agp t a = 0 - 70c; v d d = 3.3 v +/-5%; c l =10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o1 66.66 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.4 v output high current i oh1 v oh @ min = 1.0 v, v oh @ max = 3.1 -33 -33 ma output low current i ol1 v ol @ min = 1.95 v, v ol @ max= 0. 4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.92 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.58 2 ns duty cycle d t1 1 v t = 1.5 v 45 50.6 55 % skew t sk1 1 v t = 1.5 v 123 500 ps jitter t j c y c-c y c1 v t = 1.5 v 133 250 ps 1 guaranteed by design, not 100% tested in production.
17 integrated circuit systems, inc. ics950902 0475g?03/23/04 electrical characteristics - 48mhz, 24mhz t a = 0 - 70c; v d d = 3.3v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o1 v o = v dd *(0.5) 48 mhz output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 v oh @ min = 1.0 v, v oh @ max = 3.135 v -29 -23 ma output low current i ol1 v ol @ min = 1.95 v, v ol @ max= 0.4 29 27 ma rise time t r1 v ol = 0.4 v, v oh = 2.4 v 1 1.29 2 ns usb fall time t f1 v oh = 2.4 v, v ol = 0.4 v 1 1.32 2 ns duty cycle d t1 1 v t = 1.5 v 45 52.3 55 % jitter t j c y c-c y c1 v t = 1.5 v 149 350 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ref t a = 0 - 70c; v d d = 3.3 v +/-5%; c l =10-20 pf (unless otherwise stated) parameter symbol conditions min typ max units output frequency f o1 14.32 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.4 v output high current i oh1 v oh @ min = 1.0 v, v oh @ max = 3.1 -29 -23 ma output low current i ol1 v ol @ min = 1.95 v, v ol @ max= 0. 4 29 27 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 1 1.93 4 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 1 1.97 4 ns duty cycle d t1 1 v t = 1.5 v 45 54 55 % jitter t j c y c-c y c v t = 1.5 v 186 500 ps 1 guaranteed by design, not 100% tested in production.
18 integrated circuit systems, inc. ics950902 0475g?03/23/04 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
19 integrated circuit systems, inc. ics950902 0475g?03/23/04 index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l 300 mil ssop package min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 56 18.31 18.55 .720 .730 10-0034 reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) see variations see variations 0.635 basic 0.025 basic symbol in millimeters in inches common dimensions common dimensions ordering information ics950902 y flf-t example: designation for tape and reel packaging lead free (optional) package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f lf- t
20 integrated circuit systems, inc. ics950902 0475g?03/23/04 ordering information ics950902 y glf-t min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol in millimeters in inches common dimensions common dimensions index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c example: designation for tape and reel packaging lead free (optional) package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y g lf- t

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